1. Field of the Disclosure
The present disclosure relates generally to analysis of circuit designs, and more particularly to data propagation analysis for debugging circuit designs.
2. Description of Related Art
As the complexity in circuit design has increased, there has been a corresponding need for improvements in various kinds of analysis and debugging techniques. In fact, these analysis and debugging techniques have evolved from relatively simple transistor circuit-level simulation (in the early 1970s) to logic gate-level simulation (in the late 1980s) to the current art that uses Register Transfer Language (RTL)-level simulation, and formal verification. RTL describes the registers of a computer or digital electronic system and the way in which data are transferred among the combinational logic between registers.
Existing verification and debugging tools are used in the design flow of a circuit. The design flow begins with the creation of a circuit design at the RTL level using RTL source code. The RTL source code is specified according to a Hardware Description Language (HDL), such as Verilog HDL or VHDL. Circuit designers use high-level hardware description languages because of the size and complexity of modern integrated circuits. Circuit designs are developed in a high-level language using computer-implemented software applications, which enable a user to use text-editing and graphical tools to create a HDL-based design.
Conventional verification tools generate large amounts of data, such waveforms that are displayed to a circuit designer. As design complexity increases, it becomes harder and harder for circuit designers analyzing these waveforms to comprehend the activities exercised in the circuit design, since it involves looking at thousands of signals and thousands of cycles. One example of this complexity is in the analysis of a deadlock error in a system on chip (SoC) design. A waveform showing a deadlock would include activities in many circuit components interacting through an off-chip network or network on a chip, and understanding why the deadlock occurs by looking at each of the many signals and cycles in the waveform would be unproductive.